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Unfortunately, someВ design traits really do affect our compiler. Such IRs are helpful in Mesa, the machine-independent NIR facilitates sharing of powerful optimizations across drivers. So what if the IR is entirely machine-independent, compiling in the abstract and converting to the machine-specific form at the very end. On Bifrost, for example, most operations have multiple unrelated encodings this design would force much of the compiler to be duplicated. Worse, the machine irregularities will permeate every aspect of the compiler since they are now embedded into the IR. For final assembly, we will always need to pack the machine formats, but with this design, we alsoВ need to unpackВ them. Further, they are tightly packed to be small instead of simple. Unfortunately, real world instructions sets are irregular and as quirky as their compilersвЂ™ developers.

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The initial NIR-to-BIR pass is a bit harder than with abstract instructions, but final code generation is trivial, since the packing is already done.

ItвЂ™s tempting, and for simple architectures, it can work. We could reuse the hardwareвЂ™s instruction format as-is, with abstract variables instead of registers. Typically backends use a вЂњflatвЂќ IR: a list of blocks, where each block contains a list of instructions. Both Intel and AMD GPU compilers have required ground-up rewrites to fix IR issues, so I was eager to get the Bifrost IR (BIR) right to begin.ДЄn IR is simply a set of data structures representing a program. Further, IR design permeates every aspect of the compiler, so IR changes to a mature compiler are difficult. There is no one-size-fits-all IR the design necessarily is built to make certain compiler passes (like algebraic optimization) simple at the expense of others (like register allocation), justifying the use of multiple IRs within a compiler. A poor IR design can impede the growth and harm the performance of the entire compiler, while a well-designed IR enables complex features to be implemented naturally with simple, fast code. Backends convert NIR to a custom backend IR, whose design seals the fate of a compiler. In Mesa, OpenGL shaders are parsed into GLSL IR вЂ“ a tree IR expressing language-visible types вЂ“ which is converted to NIR вЂ“ a flat static single assignment IR enabling powerful optimizations. Bifrost Intermediate RepresentationДЄt the heart of a modern compiler is one or more Intermediate Representations (IRs). This redesign promises better performance - and a redesign of PanfrostвЂ™s compiler, too. Bifrost has 2 blocks вЂ“ fused multiply-add and add вЂ“ pipelined without parallelism. 64-bit operation requires a special half-performance mode. 32-bit operations are purely scalar, 16-bit/2-channel and 8-bit/4-channel SIMD. Likewise, scheduling for VLIW architectures is difficult and slots often go unused, again wasting resources and preventing shaders from reaching peak architectural performance. Automatic vectorization is difficult if a shader uses a 3-channel 32-bit vector ( vec3), most likely the extra channel will go unused, wasting resources.

In practice, these architectures are extremely difficult to compile efficiently for. Vector and VLIW architectures promise high-performance in theory, and in theory, theory and practice are the same. 5 blocks вЂ“ scalar/vector add/multiply and special function unit вЂ“ operate with partial parallelism across 2 pipeline stages. 128-bit arithmetic logic unit (ALU) allows 32-bit 4-channel SIMD. MidgardвЂ™s architecture is characterized as:

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Indeed, squinting command stream traces from Midgard and Bifrost look similar вЂ“ but the long tail of minor updates implies a nontrivial Panfrost port.Д«ut the Bifrost instruction set, on the other hand? A rather different story.Д«ifrostвЂ™s instruction set was redesigned completely from MidgardвЂ™s, requiring us to build a free software compiler targeting Bifrost from scratch. The largest changes involve the interfaces between the shaders and the command stream, including the titular shader descriptors. After all, both architectures feature approximately the same OpenGL and Vulkan capabilities, and the fixed-function hardware has not required much driver-visible optimization.

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Thus the GPU driver contains two major components, generating the command stream and compiling programs respectively.ДЇrom Midgard to Bifrost, there have been few changes to the command stream.

By contrast, the instruction set encodes the shaders themselves, as with any programmable architecture. The command stream controls the hardware, dispatching shaders and containing the state required by OpenGL or Vulkan. The interface to a modern GPU has two components, the fixed-function command stream and the programmable instruction set architecture.

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